#ifndef LS7A_CONFIG_
#define LS7A_CONFIG_

#define LS7A_UC_ACC
//#define OVRD_SATA_PHY

#define LS7A_PLL_DIV_REFC_OFFSET 0
#define LS7A_PLL_LOCK_OFFSET    7
#define LS7A_PLL_SEL0_OFFSET    8
#define LS7A_PLL_SEL1_OFFSET    9
#define LS7A_PLL_SEL2_OFFSET    10
#define LS7A_PLL_SET_OFFSET     11
#define LS7A_PLL_BYPASS_OFFSET  12
#define LS7A_PLL_PD_OFFSET      13

#define LS7A_PLL_DIV0_OFFSET    0
#define LS7A_PLL_DIV1_OFFSET    7
#define LS7A_PLL_DIV2_OFFSET    14
#define LS7A_PLL_LOOPC_OFFSET   21

#define LS7A_PLL_VALUE(LOOPC, DIV2, DIV1, DIV0) ((LOOPC << LS7A_PLL_LOOPC_OFFSET) | (DIV2 << LS7A_PLL_DIV2_OFFSET) | (DIV1 << LS7A_PLL_DIV1_OFFSET) | (DIV0 << LS7A_PLL_DIV0_OFFSET))

#define HT1_CONF_BASE_ADDR  0x90000efdfe000000
#define HT1_IO_BASE_ADDR    0x90000efdfc000000
#define HT1_MEM_BASE_ADDR   0x90000e0000000000

#define UART_BASE_ADDR_OFFSET   0x00000
#define I2C_BASE_ADDR_OFFSET    0x10000
#define PWM_BASE_ADDR_OFFSET    0x20000
#define ACPI_BASE_ADDR_OFFSET   0x50000
#define GPIO_BASE_ADDR_OFFSET   0x60000

#define INT_BASE_ADDR           0x10000000
#define HPET_BASE_ADDR          0x10001000
#define LPC_CNTL_BASE_ADDR      0x10002000
#define CONFBUS_BASE_ADDR       0x10010000
#define MISC_BASE_ADDR          0x10080000
#define LPC_MEM_BASE_ADDR       0x12000000

#define LS7A_CONFBUS_BASE_ADDR  (HT1_MEM_BASE_ADDR | CONFBUS_BASE_ADDR)
#define LS7A_MISC_BASE_ADDR     (HT1_MEM_BASE_ADDR | MISC_BASE_ADDR)

#define TEMP_GMEM_ADDR  0x40000000
#define LS7A_GMEM_TEMP_ADDR (HT1_MEM_BASE_ADDR | TEMP_GMEM_ADDR)
//confbus address
#define CONF_HT_CLKEN_OFFSET    0x418
#define CONF_HT_ROUTE_OFFSET    0x41c
#define CONF_NB_OFFSET      0x420
#define CONF_SB_OFFSET      0x430
#define CONF_PAD_OFFSET     0x438
#define CONF_PLL0_OFFSET    0x480
#define CONF_PLL1_OFFSET    0x490
#define CONF_PLL2_OFFSET    0x4a0
#define CONF_PLL3_OFFSET    0x4b0
#define CONF_PLL4_OFFSET    0x4c0
#define CONF_CHIP_ID_OFFSET 0x3ff8
//configure offset
#define CONF_DEFAULT_ROUTE_SB_OFFSET    0
#define CONF_DEFAULT_ROUTE_NB_OFFSET    0
#define CONF_SOFT_RESET_GPU_OFFSET      4
#define CONF_DISABLE_GMEM_CONFSPACE_OFFSET    8

//PAD sel inner offset
#define HDA_ENABLE_OFFSET   11
#define AC97_ENABLE_OFFSET  12
#define UART_ENABLE_OFFSET  28

#define HEADER_ADDR(X,Y)   (HT1_CONF_BASE_ADDR | (X << 11) | (Y << 8))

#define MISC_HEADER_ADDR        HEADER_ADDR(2, 0)
#define GMAC0_HEADER_ADDR       HEADER_ADDR(3, 0)
#define GMAC1_HEADER_ADDR       HEADER_ADDR(3, 1)
#define USB0_OHCI_HEADER_ADDR   HEADER_ADDR(4, 0)
#define USB0_EHCI_HEADER_ADDR   HEADER_ADDR(4, 1)
#define USB1_OHCI_HEADER_ADDR   HEADER_ADDR(4, 0)
#define USB1_EHCI_HEADER_ADDR   HEADER_ADDR(4, 1)
#define GPU_HEADER_ADDR         HEADER_ADDR(6, 0)
#define DC_HEADER_ADDR          HEADER_ADDR(6, 1)
#define HDA_HEADER_ADDR         HEADER_ADDR(7, 0)
#define AC97_HEADER_ADDR        HEADER_ADDR(7, 1)
#define SATA0_HEADER_ADDR       HEADER_ADDR(8, 0)
#define SATA1_HEADER_ADDR       HEADER_ADDR(8, 1)
#define SATA2_HEADER_ADDR       HEADER_ADDR(8, 2)
#define CONFBUS_HEADER_ADDR     HEADER_ADDR(21, 0)
#define SPI_HEADER_ADDR         HEADER_ADDR(22, 0)
#define LPC_HEADER_ADDR         HEADER_ADDR(23, 0)

#define GPIO0_OEN_OFFSET          0x00
#define GPIO1_OEN_OFFSET          0x08
#define GPIO0_O_OFFSET            0x10
#define GPIO1_O_OFFSET            0x18
#define GPIO0_I_OFFSET            0x20
#define GPIO1_I_OFFSET            0x28
#define GPIO0_INT_OFFSET          0x30
#define GPIO1_INT_OFFSET          0x38

#define GPIO_OEN_OFFSET          0x800
#define GPIO_O_OFFSET            0x900
#define GPIO_I_OFFSET            0xa00
#define GPIO_INT_OFFSET          0xb00
#endif
